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| Family ULTRA37000TM CPLD Family[1] 5V, 3.3V, ISRTM High-Performance CPLDs Features * In-System ReprogrammableTM (ISRTM) CMOS CPLDs -- JTAG interface for reconfigurability -- Design changes don't cause pinout changes -- Design changes don't cause timing changes * High density -- 32 to 512 macrocells -- 32 to 264 I/O pins -- 5 dedicated inputs including 4 clock pins * Simple timing model -- No fanout delays -- No expander delays -- No dedicated vs. I/O pin delays -- No additional delay through PIM -- No penalty for using full 16 product terms * * * * -- No delay for steering or sharing product terms 3.3V and 5V versions PCI Compatible[2] Programmable Bus-Hold capabilities on all I/Os Intelligent product term allocator provides: -- 0 to 16 product terms to any macrocell -- Product term steering on an individual basis -- Product term sharing among local macrocells * Flexible clocking -- 4 synchronous clocks per device -- Product Term clocking -- Clock polarity control per logic block * Consistent package/pinout offering across all densities -- Simplifies design migration -- Same pinout for 3.3V and 5.0V devices * Packages -- 44 to 400 Leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages General Description The ULTRA37000TM family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The ULTRA37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs. All of the ULTRA37000 devices are electrically erasable and InSystem Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the ULTRA37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The ULTRA37000 family features user programmable bus-hold capabilities on all I/Os. ULTRA37000 5.0V Devices The ULTRA37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. V CCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming. ULTRA37000V 3.3V Devices Devices operating with a 3.3V supply require 3.3V on all VCCO pins, reducing the device's power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V tolerant. These devices allow 3.3V ISR programming. Notes: 1. The data sheet parameters are final for the following devices: CY37032, CY37032V (with the exception of the 154-MHz speed bin), CY37128, CY37128V (with the exception of the 154-MHz speed bin), CY37192, CY37192V, CY37256, and CY37256V (with the exception of the 143-MHz speed bin). The data sheet parameters are considered preliminary for the following devices: CY37064, CY37064V, CY37384, CY37384V, CY37512, and CY37512V. 2. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH=2V. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 February 9, 2000 ULTRA37000TM CPLD Family[1] Selection Guide 5.0V Selection Guide General Information Device CY37032 CY37064 CY37128 CY37192 CY37256 CY37384 CY37512 Speed Bins Device CY37032 CY37064 CY37128 CY37192 CY37256 CY37384 CY37512 200 X X X X X 167 154 X X 143 125 X X X X X X X X X X X X X X 100 83 66 Macrocells 32 64 128 192 256 384 512 Dedicated Inputs 5 5 5 5 5 5 5 I/O Pins 32 32/64 64/128 120 128/160/192 160/192 160/192/264 Speed (tPD) 6 6 6.5 7.5 7.5 10 10 Speed (fMAX) 200 200 167 154 154 125 125 Device-Package Offering & I/O Count Device CY37032 CY37064 CY37128 CY37192 CY37256 CY37384 CY37512 44Lead TQFP 37 37 44Lead PLCC 37 37 37 69 69 69 69 69 133 125 133 133 165 165 165 165 197 197 197 269 44Lead CLCC 84Lead PLCC 84Lead CLCC 100Lead TQFP 160Lead TQFP 160Lead CQFP 208Lead PQFP 208Lead CQFP 256Lead BGA 352Lead BGA 2 ULTRA37000TM CPLD Family[1] 3.3V Selection Guide General Information Device CY37032V CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Speed Bins Device CY37032V[1] CY37064V[1] CY37128V[1] CY37192V CY37256V[1] CY37384V CY37512V[1] Shaded areas indicate preliminary speed bins. Macrocells 32 64 128 192 256 384 512 Dedicated Inputs 5 5 5 5 5 5 5 I/O Pins 32 32/64 64/80/128 120 128/160/192 160/192 160/192/264 Speed (tPD) 8.5 8.5 10 12 12 15 15 Speed (fMAX) 143 143 125 100 100 83 83 200 167 154 X X X 143 X X 125 100 X X 83 66 X X X X X X X X X X X X Device-Package Offering & I/O Count Device CY37032V CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V 44Lead TQFP 44Lead PLCC 44Lead CLCC 48Lead FBGA 84Lead PLCC 84Lead CLCC 100Lead TQFP 100Lead FBGA 160Lead TQFP 160Lead CQFP 208Lead PQFP 208Lead CQFP 256Lead BGA 256Lead FBGA 352Lead BGA 400Lead FBGA 37 37 37 37 37 37 69 69 69 69 69 85 133 125 133 133 165 165 165 165 197 197 197 269 269 197 3 ULTRA37000TM CPLD Family[1] Architecture Overview of ULTRA37000 Family Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations. The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives 36 inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the ULTRA37000 family. An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing parameters on the ULTRA37000 devices. The worst-case PIM delays are incorporated in all appropriate ULTRA37000 specifications. Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software--no hand routing is necessary. WarpTM and third-party development packages automatically route designs for the ULTRA37000 family in a matter of minutes. Finally, the rich routing resources of the ULTRA37000 family accommodate last minute logic changes while maintaining fixed pin assignments. Logic Block The logic block is the basic building block of the ULTRA37000 architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 1 for the block diagram. Product Term Array Each logic block features a 72 x 87 programmable product term array. This array accepts 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE) product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block. The other two OE product terms are available to the lower half of the I/O macrocells in a logic block. The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array. 3 0-16 PRODUCT TERMS 2 I/O CELL 0 2 MACROCELL 0 MACROCELL 1 7 0-16 PRODUCT TERMS to cells 2, 4, 6 8, 10, 12 FROM PIM 36 72 x 87 PRODUCT TERM ARRAY 80 PRODUCT TERM ALLOCATOR 0-16 PRODUCT TERMS MACROCELL 14 MACROCELL 15 I/O CELL 14 0-16 TO PIM PRODUCT TERMS 16 8 Figure 1. Logic Block with 50% Buried Macrocells 4 ULTRA37000TM CPLD Family[1] Low-Power Option Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block by logic block basis. Product Term Allocator Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to the other. On ULTRA37000 devices, product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The ULTRA37000 product term allocator allows sharing across groups of four output macrocells in a variable fashion. The software automatically takes advantage of this capability--the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the ULTRA37000 devices. ULTRA37000 Macrocell Within each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device. Buried Macrocell Figure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch. The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression. Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level. The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. I/O Macrocell Figure 2 illustrates the architecture of the I/O macrocell. The I/O macrocell supports the same functions as the buried macrocell with the addition of I/O capability. At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many applications. The ULTRA37000 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input. Bus Hold Capabilities on all I/Os Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application note "Understanding Bus-hold - A Feature of Cypress CPLDs." Programmable Slew Rate Control Each output has a programmable configuration bit, which sets the output slew rate to fast or slow. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance. 5 ULTRA37000TM CPLD Family[1] f I/O MACROCELL FROM PTM 0-16 PRODUCT TERMS C25 0 1 FAST SLEW SLOW 0 P D/T/L O Q 1 0 1 C4 DECODE "0" "1" 0 1 2 3 O O C26 I/O CELL 0 1 2 3 O R 4 C0 C1 C24 1 0 C6 C5 C2 C3 BURIED MACROCELL FROM PTM 0-16 PRODUCT TERMS 0 1 C25 0 0 1 2 3 1 Q C7 R DECODE C0 C1 C24 0 O P D/T/L Q 1 O 4 1 0 C2 C3 FEEDBACK TO PIM FEEDBACK TO PIM FEEDBACK TO PIM ASYNCHRONOUS BLOCK RESET 4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3) ASYNCHRONOUS 1 ASYNCHRONOUS CLOCK(PTCLK) BLOCK PRESET OE0 OE1 Figure 2. I/O and Buried Macrocells INPUT PIN 0 1 2 3 C12 C13 O TO PIM FROM CLOCK POLARITY MUXES 0 1 2 3 C10 C11 D O Q D Q D LE Q Figure 3. Input Macrocell 6 ULTRA37000TM CPLD Family[1] 0 1 INPUT/CLOCK PIN C12 O TO CLOCK MUX ON ALL INPUT MACROCELLS 0 O 1 TO CLOCK MUX IN EACH LOGIC BLOCK OR C16 CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUT FROM CLOCK POLARITY INPUT CLOCK PINS 0 1 2 3 C8 C9 D O Q D Q 0 1 2 3 C10C11 C13, C14, C15 O TO PIM D LE Q Figure 4. Input/Clock Macrocell Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks. Dedicated Inputs/Clocks Five pins on each member of the ULTRA37000 family are designated as input-only. There are two types of dedicated inputs on ULTRA37000 devices: input pins and input/clock pins. Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, doubleregistered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control. Figure 4 illustrates the architecture for the input/clock pins. Like the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity. Product Term Clocking In addition to the four synchronous clocks, the ULTRA37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection. Timing Model One of the most important features of the ULTRA37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input setup time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used. INPUT The ULTRA37000 features: * No fanout delays * No expander delays * No dedicated vs. I/O pin delays * No additional delay through PIM * No penalty for using 0-16 product terms * No added delay for steering product terms * No added delay for sharing product terms * No routing delays * No output bypass delays The simple timing model of the ULTRA37000 family eliminates unexpected performance penalties. COMBINATORIAL SIGNAL INPUT tPD = 6.5 ns REGISTERED SIGNAL tS = 3.5 ns D,T,L O OUTPUT tCO = 4.5 ns OUTPUT CLOCK Figure 5. Timing Model for CY37128 JTAG and PCI Standards PCI Compliance 5V operation of the ULTRA37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The ULTRA37000 family's simple and predictable timing model ensures compliance with the PCI AC specifications independent of the design. 7 ULTRA37000TM CPLD Family[1] IEEE 1149.1 Compliant JTAG The ULTRA37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR. Boundary Scan The ULTRA37000 family supports Bypass, Sample/Preload, Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 6. Instruction Register TDI TDO Verilog design entry, VHDL waveform simulation (SpeedWaveTM), a VHDL debugger, and VHDL synthesis, all integrated in a graphical design environment. Warp3 is available on PCs using Windows(R), Windows95, or Windows NT and on Sun and Hewlett Packard workstations. See the Warp3 data sheet for further information. Third-Party Software Cypress products are supported in a number of third-party design entry and simulation tools. All major third-party software vendors provide support for the ULTRA37000 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors. Programming There are four programming options available for ULTRA37000 devices. The first method is to use a PC with the 37000 UltraISR programming cable and software. With this method, the ISR pins of the ULTRA37000 devices are routed to a connector at the edge of the printed circuit board. The 37000 UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on each of the ULTRA37000 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions. For more information on the Cypress ISR Interface, see the ISR Programming Kit data sheet (CY3700i). The second method for programming ULTRA37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information. The third programming option for ULTRA37000 devices is to utilize the embedded controller or processor that already exists in the system. The ULTRA37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed. The embedded controller then simply directs this ISR stream to the chain of ULTRA37000 devices to complete the desired reconfiguring or diagnostic operations. Contact your local sales office for information on availability of this option. The fourth method for programming ULTRA37000 devices is to use the same programmer that is currently being used to program FLASH370i devices. For all pinout, electrical, and timing requirements, refer to device data sheets. For ISR cable and software specifications, refer to the UltraISR kit data sheet (CY3700i). Third-Party Programmers As with development software, Cypress support is available on a wide variety of third-party programmers. All major third-party programmers (including BP Micro, Data I/O, and SMS) support the ULTRA37000 family. TMS TCLK JTAG TAP CONTROLLER Bypass Reg. Boundary Scan idcode Usercode ISR Prog. Data Registers Figure 6. JTAG Interface In-System Reprogramming (ISR) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The ULTRA37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. Development Software Support Warp2 Warp2 is a state-of-the-art HDL compiler for designing with Cypress programmable logic. Warp2 utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware Description Language (HDL) for design entry. Warp2 accepts VHDL or Verilog input, synthesizes and optimizes the entered design, and outputs a JEDEC map for the desired ULTRA37000 device. For simulation, Warp2 provides a graphical waveform simulator as well as VHDL and Verilog Timing Models. VHDL and Verilog are open, powerful, non-proprietary Hardware Description Languages (HDLs) that are standards for behavioral design entry and simulation. HDL allows designers to learn a single language that is useful for all facets of the design process. See the Warp2 data sheet (CY3120 /CY3110) for further information. Warp3 Warp3 is a sophisticated development system that is based on the latest version of Viewlogic's CAE design environment. Warp3 features schematic capture (ViewDrawTM), VHDL and 8 ULTRA37000TM CPLD Family[1] Logic Block Diagrams CY37032 / CY37032V Clock/ Input Input 1 4 TDI TCLK TMS JTAG Tap Controller TDO 4 I/O0-I/O15 16 I/Os LOGIC BLOCK A 16 36 16 36 4 JTAGEN 16 I/Os I/O16-I/O31 PIM 16 LOGIC BLOCK B 16 CY37064 / CY37064V (100-Lead TQFP) Clock/ Input Input 1 4 4 36 I/O0-I/O 15 16 I/Os LOGIC BLOCK A LOGIC BLOCK B 16 36 16 I/Os I/O 16-I/O 31 16 36 16 4 PIM LOGIC BLOCK D LOGIC BLOCK C 16 I/Os I/O 48-I/O63 36 16 I/Os I/O 32-I/O47 16 32 TDI TCLK TMS JTAG Tap Controller TDO 32 9 ULTRA37000TM CPLD Family[1] Logic Block Diagrams (continued) CY37128 / CY37128V (160-Lead TQFP) TDI CLOCK INPUTS INPUTS 1 INPUT MACROCELL 4 I/O0-I/O15 16 I/Os LOGIC BLOCK 36 16 36 16 36 16 36 16 PIM 4 INPUT/CLOCK MACROCELLS 4 36 16 36 16 36 16 36 16 LOGIC BLOCK JTAG Tap Controller TDO TCLK TMS JTAGEN 16 I/Os I/O112-I/O127 A H 16 I/Os I/O16-I/O31 16 I/Os I/O32-I/O47 LOGIC BLOCK B LOGIC BLOCK 16 I/Os I/O96-I/O111 16 I/Os I/O80-I/O95 G LOGIC BLOCK LOGIC BLOCK C 16 I/Os LOGIC BLOCK F LOGIC BLOCK 16 I/Os I/O28-I/O63 D E I/O64-I/O79 64 64 CY37192 / CY37192V (160-Lead TQFP) Clock/ Input Input 1 4 4 36 10 I/Os I/O 0-I/O9 10 I/Os I/O 10-I/O 19 10 I/Os I/O 20-I/O 29 10 I/Os I/O 30-I/O 39 10 I/Os I/O 40-I/O 49 10 I/Os I/O 50-I/O 59 LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK F 60 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 4 LOGIC BLOCK L LOGIC BLOCK K LOGIC BLOCK J LOGIC BLOCK I LOGIC BLOCK H LOGIC BLOCK G 60 10 I/Os I/O 110-I/O 119 10 I/Os I/O 100-I/O 109 10 I/Os I/O 90 -I/O99 10 I/Os I/O 80 -I/O89 10 I/Os I/O 70 -I/O79 10 I/Os I/O 60 -I/O69 PIM 36 16 36 16 36 16 TDI TCLK TMS JTAG Tap Controller TDO 10 ULTRA37000TM CPLD Family[1] Logic Block Diagrams (continued) CY37256 / CY37256V (256-Lead BGA) Clock/ Input Input 1 4 4 12 I/Os I/O0-I/O11 I/O12-I/O23 12 I/Os LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK F LOGIC BLOCK G LOGIC BLOCK H 96 TDO 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 4 LOGIC BLOCK P LOGIC BLOCK O LOGIC BLOCK N LOGIC BLOCK M LOGIC BLOCK L LOGIC BLOCK K LOGIC BLOCK J LOGIC BLOCK I 96 12 I/Os I/O180-I/O191 12 I/Os I/O168-I/O179 12 I/Os I/O156-I/O167 12 I/Os I/O144-I/O155 12 I/Os I/O132-I/O143 12 I/Os I/O120-I/O131 12 I/Os I/O108-I/O119 12 I/Os I/O96-I/O107 12 I/Os I/O24-I/O35 I/O36-I/O47 12 I/Os 12 I/Os I/O48-I/O59 12 I/Os I/O60-I/O71 12 I/Os I/O72-I/O83 12 I/Os I/O84-I/O95 TDI TCLK TMS PIM 36 16 36 16 36 16 36 16 JTAG Tap Controller 11 ULTRA37000TM CPLD Family[1] Logic Block Diagrams (continued) CY37384 / CY37384V (256-Lead BGA) Clock/ Input Input 1 4 4 12 I/Os I/O0-I/O11 12 I/Os I/O12-I/O23 I/O24-I/O35 12 I/Os LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O36 -I/O47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O48-I/O59 12 I/Os I/O60-I/O71 12 I/Os I/O72-I/O83 LOGIC BLOCK AG LOGIC BLOCK AH LOGIC BLOCK AI LOGIC BLOCK AJ 12 I/Os I/O84-I/O95 LOGIC BLOCK AK LOGIC BLOCK AL TDI TCLK TMS 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 4 LOGIC BLOCK BL LOGIC BLOCK BK LOGIC BLOCK BJ LOGIC BLOCK BI LOGIC BLOCK BH LOGIC BLOCK BG LOGIC BLOCK BF LOGIC BLOCK BE LOGIC BLOCK BD LOGIC BLOCK BC LOGIC BLOCK BB LOGIC BLOCK BA 12 I/Os I/O96-I/O107 12 I/Os I/O120-I/O143 12 I/Os I/O108-I/O131 12 I/Os I/O96-I/O119 12 I/Os I/O132-I/O155 12 I/Os I/O168-I/O191 12 I/Os I/O156-I/O179 12 I/Os I/O144-I/O167 PIM 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 JTAG Tap Controller TDO 96 96 12 ULTRA37000TM CPLD Family[1] Logic Block Diagrams (continued) CY37512 / CY37512V (352-Lead BGA) Input Clock/ Input 4 1 4 36 12 I/Os I/O 0-I/O 11 12 I/Os I/O 12-I/O 23 12 I/Os I/O 24-I/O 35 LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O 36-I/O 47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O 48-I/O 59 LOGIC BLOCK AG LOGIC BLOCK AH 12 I/Os I/O 60-I/O 71 LOGIC BLOCK AI LOGIC BLOCK AJ 12 I/Os I/O 72-I/O 83 12 I/Os I/O 84-I/O 95 12 I/Os I/O 96-I/O 107 12 I/Os I/O 108-I/O 119 12 I/Os I/O 120-I/O 131 LOGIC BLOCK AK LOGIC BLOCK AL LOGIC BLOCK AM LOGIC BLOCK AN LOGIC BLOCK AO LOGIC BLOCK AP 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 4 LOGIC BLOCK BP LOGIC BLOCK BO LOGIC BLOCK BN LOGIC BLOCK BM LOGIC BLOCK BL LOGIC BLOCK BK LOGIC BLOCK BJ LOGIC BLOCK BI LOGIC BLOCK BH LOGIC BLOCK BG LOGIC BLOCK BF LOGIC BLOCK BE LOGIC BLOCK BD LOGIC BLOCK BC LOGIC BLOCK BB LOGIC BLOCK BA 12 I/Os I/O 180-I/O 191 12 I/Os I/O 168-I/O 179 12 I/Os I/O 156-I/O 167 12 I/Os I/O 144-I/O 155 12 I/Os I/O 132-I/O 143 12 I/Os I/O 192-I/O 203 12 I/Os I/O 204-I/O 215 12 I/Os I/O216-I/O 227 12 I/Os I/O252-I/O 263 12 I/Os I/O240-I/O 251 12 I/Os I/O228-I/O 239 PIM 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 132 TDI TCLK TMS JTAG Tap Controller TDO 132 13 ULTRA37000TM CPLD Family[1] 5.0V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V DC Program Voltage............................................. 4.5 to 5.5V Current into Outputs .................................................... 16 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range[3] Range Commercial Industrial Military[4] Ambient Temperature[3] 0C to +70C -40C to +85C -55C to +125C Junction Temperature 0C to +90C -40C to +105C -55C to +130C Output Condition 5V 3.3V 5V 3.3V 5V 3.3V VCC 5V 0.25V 5V 0.25V 5V 0.5V 5V 0.5V 5V 0.5V 5V 0.5V VCCO 5V 0.25V 3.3V 0.3V 5V 0.5V 3.3V 0.3V 5V 0.5V 3.3V 0.3V Notes: 3. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the ULTRA37000 Family devices, please refer to the Application Note titled "An Introduction to In System Reprogramming with the ULTRA37000." 4. TA is the "Instant On" case temperature. 14 ULTRA37000TM CPLD Family[1] 5.0V Device Electrical Characteristics Over the Operating Range Parameter VOH VOHZ Description Output HIGH Voltage Output HIGH Voltage with Output Disabled[9] VCC = Min. Test Conditions IOH = -3.2 mA (Com'l/Ind)[5] IOH = -2.0 mA (Mil) VCC = Max. IOH = 0 A (Com'l) [5] [6] Min. 2.4 2.4 Typ. Max. Unit V V 4.2 4.5 [6] [6] [5] V V V V V V V V A A A mA A A IOH = 0 A (Ind/Mil)[6] IOH = -100 A (Com'l) IOH = -150 A (Ind/Mil) 3.6 3.6 0.5 0.5 2.0 -0.5 -10 -50 0 -30 +75 -75 +500 -500 -70 VCCmax 0.8 10 50 -125 -160 VOL VIH VIL IIX IOZ IOZBH IOS IBHL IBHH IBHLO IBHHO Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Leakage Current Output Short Circuit Current[8, 9] Input Bus-Hold LOW Sustaining Current Input Bus-Hold HIGH Sustaining Current Input Bus-Hold LOW Overdrive Current Input Bus-Hold HIGH Overdrive Current VCC = Min. IOL = 16 mA (Com'l/Ind) IOL = 12 mA (Mil)[5] Guaranteed Input Logical HIGH Voltage for all Inputs[7] Guaranteed Input Logical LOW Voltage for all Inputs[7] VI = GND OR VCC, Bus-Hold Disabled VO = GND or VCC, Output Disabled, Bus-Hold Disabled VCC = Max., VO = 3.3V, Output Disabled[7], Bus-Hold Enabled VCC = Max., VOUT = 0.5V VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max. A A Inductance[9] Parameter L Description Maximum Pin Inductance Test Conditions VIN = 5.0V at f = 1 MHz 44Lead TQFP 2 44Lead PLCC 5 44Lead CLCC 2 84Lead PLCC 8 84Lead CLCC 5 100Lead TQFP 8 160Lead TQFP 9 208Lead PQFP 11 Unit nH Capacitance[9] Parameter CI/O CCLK Description Input/Output Capacitance Clock Signal Capacitance Test Conditions VIN = 5.0V at f = 1 MHz at TA = 25C VIN = 5.0V at f = 1 MHz at TA = 25C Max. 8 12 Unit pF pF Endurance Characteristics[9] Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions [3] Min. 1,000 Typ. 10,000 Unit Cycles Notes: 5. I OH = -2 mA, IOL = 2 mA for TDO. 6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are output disabled during ISR programming. Refer to the application note "Understanding BusHold" for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 9. Tested initially and after any design or process changes that may affect these parameters. 15 ULTRA37000TM CPLD Family[1] 3.3V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V DC Program Voltage............................................. 3.0 to 3.6V Current into Outputs ...................................................... 8 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range[3] Range Commercial Industrial Military[4] Ambient Temperature[3] 0C to +70C -40C to +85C -55C to +125C Junction Temperature 0C to +90C -40C to +105C -55C to +130C VCC 3.3V 0.3V 3.3V 0.3V 3.3V 0.3V 3.3V Device Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ IOS IBHL IBHH IBHLO IBHHO Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[8, 9] Input Bus-Hold LOW Sustaining Current Input Bus-Hold HIGH Sustaining Current Input Bus-Hold LOW Overdrive Current Input Bus-Hold HIGH Overdrive Current VCC = Min. VCC = Min. Test Conditions IOH = -4 mA (Com'l)[5] IOH = -3 mA (Mil) IOL = 6 mA (Mil) [5] Min. 2.4 Max. Unit V IOL = 8 mA (Com'l)[5] [5] 0.5 2.0 -0.5 -10 -50 -30 +75 -75 +500 -500 5.5 0.8 10 50 -160 V V V A A mA A A A A Guaranteed Input Logical HIGH Voltage for all Inputs[7] Guaranteed Input Logical LOW Voltage for all Inputs[7] VI = GND OR VCC, Bus-Hold Disabled VO = GND or VCC, Output Disabled, Bus-Hold Disabled VCC = Max., VOUT = 0.5V VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max. Inductance[9] Parameter L Description Maximum Pin Inductance Test Conditions VIN = 3.3V at f = 1 MHz 44Lead TQFP 2 44Lead PLCC 5 44Lead CLCC 2 84Lead PLCC 8 84Lead CLCC 5 100Lead TQFP 8 160Lead TQFP 9 208Lead PQFP 11 Unit nH 16 ULTRA37000TM CPLD Family[1] Capacitance[9] Parameter CI/O CCLK Description Input/Output Capacitance Clock Signal Capacitance Test Conditions VIN = 3.3V at f = 1 MHz at TA = 25C VIN = 3.3V at f = 1 MHz at TA = 25C Max. 8 12 Unit pF pF Endurance Characteristics[9] Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions [3] Min. 1,000 Typ. 10,000 Unit Cycles AC Characteristics 5.0V AC Test Loads and Waveforms 238 (COM'L) 319 (MIL) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 170 (COM'L) 236 (MIL) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 238 (COM'L) 319 (MIL) 3.0V 90% 170 (COM'L) GND 236 (MIL) <2 ns 10% 90% 10% <2 ns ALL INPUT PULSES (a) Equivalent to: (b) (c) THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V(COM'L) OUTPUT 2.13V(MIL) 5 OR 35 pF 3.3V AC Test Loads and Waveforms 295 (COM'L) 393 (MIL) 3.3V OUTPUT 35 pF INCLUDING JIG AND SCOPE 340 (COM'L) 453 (MIL) 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE 295 (COM'L) 393 (MIL) 3.0V 90% 340 (COM'L) GND 453 (MIL) <2 ns 10% 90% 10% <2 ns ALL INPUT PULSES (a) Equivalent to: THEVENIN EQUIVALENT (b) (c) OUTPUT 158 (COM'L) 270 (MIL) 1.77V(COM'L) 1.77V(MIL) 5 OR 35 pF 17 ULTRA37000TM CPLD Family[1] Parameter[10] tER(-) VX 1.5V Output Waveform--Measurement Level VOH tER(+) 2.6V 0.5V VX VOL tEA(+) 1.5V 0.5V VX VX tEA(-) Vthe 0.5V VOH VX 0.5V VOL (d) Test Waveforms Note: 10. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load. 18 ULTRA37000TM CPLD Family[1] Switching Characteristics Over the Operating Range[11] Parameter Combinatorial Mode Parameters tPD[12, 13, 14] tPDL[12, 13, 14] tPDLL[12, 13, 14] tEA[12, 13, 14] tER[10, 12] tWL tWH tIS tIH tICO[12, 13, 14] tICOL[12, 13, 14] tCO[13, 14] tS[12] tH tCO2 [12, 13, 14] Description Input to Combinatorial Output Input to Output Through Transparent Input or Output Latch Input to Output Through Transparent Input and Output Latches Input to Output Enable Input to Output Disable Clock or Latch Enable Input LOW Time[9] Clock or Latch Enable Input HIGH Time Input Register or Latch Set-Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output Input Register Clock or Latch Enable to Output Through Transparent Output Latch Synchronous Clock (CLK 0, CLK1, CLK2, or CLK3) or Latch Enable to Output Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable Register or Latch Data Hold Time Output Synchronous Clock (CLK0, CLK 1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay (Through Logic Array) Output Synchronous Clock (CLK 0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous Clock (CLK 0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array) Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 CLK1, CLK2, or CLK3) or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable Product Term Clock or Latch Enable (PTCLK) to Output Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) Register or Latch Data Hold Time Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch Enable (PTCLK) Buried Register Used as an Input Register or Latch Data Hold Time Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) [9] Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Register Parameters Synchronous Clocking Parameters tSCS[12] tSL[12] tHL Product Term Clocking Parameters tCOPT[12, 13, 14] tSPT tHPT tISPT[12] tIHPT tCO2PT[12, 13, 14] tICS[12] ns ns ns ns ns ns Pipelined Mode Parameters Input Register Synchronous Clock (CLK 0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK 0, CLK1, CLK2, or CLK3) ns Notes: 11. All AC parameters are measured with two outputs switching and 35-pF AC Test Load. 12. Logic Blocks operating in Low-Power Mode, add tLP to this spec. 13. Outputs using Slow Output Slew Rate, add tSLEW to this spec. 14. When VCCO = 3.3V, add t3.3IO to this spec. 19 ULTRA37000TM CPLD Family[1] Switching Characteristics Over the Operating Range[11] (continued) Parameter Operating Frequency Parameters fMAX1 fMAX2 fMAX3 fMAX4 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[9] Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[9] Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)[9] Asynchronous Reset Width[9] Asynchronous Reset Recovery Time[9] Asynchronous Reset to Output Asynchronous Preset Width [9] [9] Description Unit MHz MHz MHz MHz Reset/Preset Parameters tRW tRR[12] tRO[12, 13, 14] tPW tPR [12] ns ns ns ns ns ns ns ns ns ns ns ns ns Asynchronous Preset Recovery Time Asynchronous Preset to Output Low Power Adder Slow Output Slew Rate Adder 3.3V I/O Mode Timing Adder[9] tPO[12, 13, 14] tLP tSLEW t3.3IO tS JTAG tH JTAG tCO JTAG fJTAG User Option Parameters JTAG Timing Parameters Set-Up Time from TDI and TMS to TCK [9] Hold Time on TDI and TMS [9] Falling Edge of TCK to TDO[9] Maximum JTAG Tap Controller Frequency[9] 20 ULTRA37000TM CPLD Family[1] Switching Characteristics Over the Operating Range[11] 200 MHz Max. Min. Parameter tPD[12, 13, 14] tPDL [12, 13, 14] 167 MHz Max. Min. 154 MHz Max. Min. 143 MHz Max. Min. 125 MHz Max. Min. 100 MHz Max. Min. 83 MHz Max. Min. 66 MHz Max. 20 22 24 24 24 5 5 4 4 24 26 10 10 0 24 15 15 0 20 6 6 -2 19 30 15 66 100 50 66 Min. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz Combinatorial Mode Parameters 6 11 12 8 8 2.5 2.5 2 2 11 12 4 4 0 9.5 5 7.5 0 7 2.5 2.5 -2 6 12 5 200 200 125 167 6 167 200 125 167 2.5 2.5 -2 6.5 14 6 154 200 105 154 6 7.5 0 10 2.5 2.5 -2 6.5 15 7 143 167 91 125 4 0 10 6.5 8.5 0 10 3 3 -2 7.5 19 8 125[15] 154 83 118 2.5 2.5 2 2 11 12 4 5 0 11 7 9 0 13 3 3 -2 9 19 10 100 153 80 [16] [16] 6.5 12.5 13.5 8.5 8.5 2.5 2.5 2 2 7.5 14.5 15.5 11 11 2.5 2.5 2 2 11 12 4.5 5 0 8.5 16 17 13 13 3 3 2 2 12.5 14 6 5.5 12 8[15] 10 0 [15] 10 16.5 17.5 14 14 3 3 2.5 2.5 12.5 16 6.5[15] 6 14 10 12 0 13 3 3 -2 [16] 12 17 18 16 16 4 4 3 3 16 18 6.5[16] 8 16 12 15 0 13 4.5 4.5 -2 11 21 12 83 125 [17] [17] 15 19 20 19 19 tPDLL[12, 13, 14] tEA[12, 13, 14] tER[10, 12] tWL tWH tIS tIH tICO[12, 13, 14] tICOL[12, 13, 14] tCO [13, 14] tS[12] tH tCO2[12, 13, 14] tSCS[12] tSL[12] tHL tCOPT[12, 13, 14] tSPT tHPT tISPT[12] tIHPT tCO2PT[12, 13, 14] tICS[12] fMAX1 fMAX2 fMAX3 fMAX4 Input Register Parameters 19 21 8[17] 0 19 Synchronous Clocking Parameters 0 0 Product Term Clocking Parameters 15 14 24 Pipelined Mode Parameters Operating Frequency Parameters 62.5 83 100 Notes: 15. The following values correspond to the CY37512 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, fMAX1 = 118 MHz. 16. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz. 17. The following values correspond to the CY37512V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz. 21 ULTRA37000TM CPLD Family[1] Switching Characteristics Over the Operating Range[11] (continued) 200 MHz Max. Min. Parameter tRW tRR [12] 167 MHz Max. Min. 154 MHz Max. Min. 143 MHz Max. Min. 125 MHz Max. Min. 100 MHz Max. Min. 83 MHz Max. Min. 66 MHz Max. 26 20 22 26 2.5 2.5 0.3 20 20 Min. Unit ns ns ns ns ns ns ns ns ns Reset/Preset Parameters 8 10 12 8 10 12 2.5 2.5 0.3 8 10 13 2.5 2.5 0.3 8 10 13 8 10 13 2.5 2.5 0.3 8 10 13 8 10 14 2.5 2.5 0.3 8 10 14 10 12 15 2.5 2.5 0.3 10 12 15 12 14 18 2.5 2.5 0.3 12 14 18 15 17 21 2.5 2.5 0.3 15 17 21 20 22 tRO[12, 13, 14] tPW tPR[12] tPO[12, 13, 14] tLP tSLEW t3.3IO User Option Parameters JTAG Timing Parameters tS JTAG tH JTAG tCO JTAG fJTAG 0 20 20 20 0 20 20 20 0 20 20 20 0 20 20 20 0 20 20 20 0 20 20 20 0 20 20 20 0 20 ns ns ns MHz 22 ULTRA37000TM CPLD Family[1] Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking INPUT tS SYNCHRONOUS CLOCK tCO REGISTERED OUTPUT tCO2 REGISTERED OUTPUT tH tWH SYNCHRONOUS CLOCK tWL Registered Output with Product Term Clocking Input Going Through the Array INPUT tSPT PRODUCT TERM CLOCK tCOPT REGISTERED OUTPUT tHPT 23 ULTRA37000TM CPLD Family[1] Switching Waveforms (continued) Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT tISPT PRODUCT TERM CLOCK tCO2PT REGISTERED OUTPUT tIHPT Latched Output INPUT tSL LATCH ENABLE tPDL LATCHED OUTPUT tCO tHL Registered Input REGISTERED INPUT tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tIH tWH CLOCK tWL 24 ULTRA37000TM CPLD Family[1] Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK tICS OUTPUT REGISTER CLOCK tSCS Latched Input LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH tWH LATCH ENABLE tWL Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tSL tHL tWH LATCH ENABLE tWL 25 ULTRA37000TM CPLD Family[1] Switching Waveforms (continued) Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK Output Enable/Disable INPUT tER OUTPUTS tEA 26 ULTRA37000TM CPLD Family[1] Power Consumption Typical 5.0V Power Consumption CY37032 60 H igh S p ee d 50 40 L ow P o w e r Icc (mA) 30 20 10 0 0 50 1 00 1 50 2 00 2 50 F r eq u e n c y (M H z) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature CY37064 90 80 H igh S pee d 70 60 Icc (mA) 50 Lo w P ow er 40 30 20 10 0 0 20 40 60 80 1 00 1 20 1 40 1 60 1 80 F req u en cy (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature 27 ULTRA37000TM CPLD Family[1] Typical 5.0V Power Consumption (continued) CY37128 160 140 H igh S p e e d 120 100 Icc (mA) Low Power 80 60 40 20 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature CY37192 300 250 H igh S p e e d 200 Icc (mA) 150 Low Power 100 50 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature 28 ULTRA37000TM CPLD Family[1] Typical 5.0V Power Consumption (continued) CY37256 300 H igh S p e e d 250 200 Low Power Icc (mA) 150 100 50 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature CY37384 5 00 4 50 H igh S p eed 4 00 3 50 3 00 Icc (mA) 2 50 Lo w P ow e r 2 00 1 50 1 00 50 0 0 20 40 60 80 1 00 1 20 1 40 1 60 F req u en c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature 29 ULTRA37000TM CPLD Family[1] Typical 5.0V Power Consumption (continued) CY37512 600 H igh S p e e d 500 400 Icc (mA) 300 Low Power 200 100 0 0 20 40 60 80 100 120 140 160 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature Typical 3.3V Power Consumption CY37032V 30 H igh S peed 25 Low P ow e r 20 Icc (mA) 15 10 5 0 0 20 40 60 80 10 0 12 0 14 0 16 0 Freq uen cy (M H z) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature 30 ULTRA37000TM CPLD Family[1] Typical 3.3V Power Consumption (continued) CY37064V 45 H igh S p ee d 40 35 30 L ow P ow e r Icc (mA) 25 20 15 10 5 0 0 20 40 60 80 1 00 1 20 1 40 F req u en c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature CY37128V 80 H ig h S p e e d 70 60 Low Power 50 Icc (mA) 40 30 20 10 0 0 20 40 60 80 100 120 140 F r e q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature 31 ULTRA37000TM CPLD Family[1] Typical 3.3V Power Consumption (continued) CY37192V 120 H ig h S p e e d 100 80 Low Power Icc (mA) 60 40 20 0 0 20 40 60 80 100 120 F r e q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature CY37256V 140 120 H ig h S p e e d 100 Low Power Icc (mA) 80 60 40 20 0 0 20 40 60 80 100 120 F r e q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature 32 ULTRA37000TM CPLD Family[1] Typical 3.3V Power Consumption (continued) CY37384V 200 180 H ig h S p e e d 160 140 Low Power 120 Icc (mA) 100 80 60 40 20 0 0 10 20 30 40 50 60 70 80 90 F r e q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature CY37512V 25 0 20 0 H ig h S p e e d 15 0 Low P ower Icc (mA) 10 0 50 0 0 10 20 30 40 50 60 70 80 90 F re q u e n c y (M H z) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature 33 ULTRA37000TM CPLD Family[1] Pin Configurations[18] 44-Pin TQFP (A44) Top View GND VCCO I/O31 I/O30 I/O1 I/O 0 I/O4 I/O3 I/O2 I/O29 I/O28 I/O5/TCLK I/O6 I/O 7 CLK 2/I0 JTAGEN GND CLK0/I 1 I/O8 I/O 9 I/O10 I/O11 44 43 42 41 40 39 38 37 36 35 34 33 32 2 3 31 4 30 5 29 6 28 27 7 1 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 I/O12 I/O13 /TMS I/O14 I/O15 I/O27/TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 I/O21 VCC GND I/O16 I/O17 I/O18 44-Pin PLCC (J67) / CLCC (Y67) Top View I/O31 I/O30 I/O29 I/O28 I/O27 /TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 I/O21 6 5 4 3 2 1 44 43 42 41 40 I/O 5 /TCLK I/O6 I/O7 CLK2/I0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O 11 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O /TMS 13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 /TDO I/O20 Note: 18. For 3.3V versions (ULTRA37000V), VCCO = VCC = 3.3V 0.3V. I/O 1 I/O 0 GND VCCO I/O 4 I/O 3 I/O 2 34 I/O19 /TDO I/O20 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 48-Ball Fine-Pitch BGA (BA48) Top View 1 A I/O5 TCLK VCC 2 VCC 3 I/O3 4 I/O1 5 I/O31 6 I/O30 7 VCC 8 I/O27 TDI CLK1/ I4 I3 B I/O4 I/O2 I/O0 I/O29 I/O28 I/O26 C CLK2/ I0 JTAGEN I/O7 I/O6 GND GND I/O25 I/O24 D I/O8 I/O9 GND GND I/O22 I/O23 CLK3/ I2 VCC E CLK0/ I1 I/O13 TMS I/O12 I/O11 I/O10 I/O16 I/O20 I/O21 F VCC I/O14 I/O15 I/O17 I/O18 VCC I/O19 TDO 35 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 84-Lead PLCC (J83) / CLCC (Y84) Top View JTAGEN I/O 63 62 61 60 59 58 57 I/O 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 /TDO 32 33 34 35 36 37 /TMS 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 39 53 GND I/O 55 I/O 54 /TDI I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 CLK3/I 4 GND VCCO CLK2/I 3 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 GND I/O 56 V CCO GND 1 I/O 0 GND 7 6 5 4 3 2 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 38 11 10 I/O 8 I/O 9 I/O10 /TCLK I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CLK0/I 0 VCCO GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 I/O 24 I/O 25 GND VCCO [19] I 2 I/O I/O I/O I/O I/O Note: 19. This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility, I/O 36 VCC I/O I/O ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 100-Lead TQFP (A100) Top View I/O 63 62 61 I/O 60 59 58 57 VCCO 1 I/O 0 VCCO GND VCC N/C 56 GND 7 6 5 4 3 NC 2 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TCLK GND I/O I/O 8 9 I/O NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TDI VCCO I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 CLK 3 /I 4 GND NC VCCO CLK 2 /I 3 I/ O47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 GND NC I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CLK0 /I 0 VCCO N/C GND CLK 1 /I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCCO NC TMS GND VCC I/O 32 I/O 33 [19] I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 39 GND I2 VCCO 37 VCCO TDO NC ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 100-Ball Fine-Pitch BGA (BB100) Top View 1 A NC 2 I/O9 3 I/O8 4 I/O6 5 I/O3 6 I/O76 7 I/O74 8 I/O72 9 I/O71 10 I/O70 B I/O11 I/O10 I/O7 I/O5 I/O2 I/O77 VCC I/O73 I/O68 I/O69 C I/O12 I/O13 TCLK VCC VCC I/O4 I/O1 I/O78 I/O75 VCC I/O67 TDI CLK3/ I4 CLK2/ I3 I2 I/O66 D I/O14 I/O15 I/O16 I/O0 I/O79 I/O63 I/O64 I/O65 E I/O17 CLK0/ I0 JTAGEN I/O18 I/O19 GND GND I/O60 I/O61 I/O62 F I/O22 I/O21 I/O20 GND GND I/O59 I/O58 I/O57 G I/O27 CLK1/ I1 I/O33 TMS I/O32 I/O26 I/O24 I/O23 I/O56 I/O55 I/O54 VCC I/O53 H I/O28 VCC I/O25 I/O39 I/O40 I/O52 VCC I/O47 TDO I/O48 I/O51 J I/O29 I/O35 VCC I/O38 I/O41 I/O43 I/O45 I/O50 K I/O30 I/O31 I/O34 I/O36 I/O37 I/O42 I/O44 I/O46 I/O49 NC 38 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 160-Lead TQFP (A160) / CQFP (U162) Top View VCCO I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCCO GND VCC JTAGEN I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND GND I/O16 I/O17 I/O18 I/O19 I/O20/TCLK I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 CLK0/I 0 VCCO GND CLK1/I 1 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VCCO I/O111 I/O110 I/O109 I/O108 /TDI I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 CLK3 /I4 GND VCCO CLK2 /I3 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 GND GND I/O48 I/O49 I/O50 I/O51 I/O52/TMS I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCCO GND VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I/O79 VCCO 39 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 208-Lead PQFP (N208) / CQFP (U208) / EQFP (NT208) Top View GND I/O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 I2 VCC0 GND VCC I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 GND I/O90 I/O91 I/O92 I/O93 I/O94 GND TDO I/O95 I/O96 I/O97 I/O98 I/O99 VCC0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 GND I/O20 I/O21 I/O22 I/O23 I/O24 TCLK I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 I/O31 I/O32 I/O33 I/O34 NC I/O35 I/O36 I/O37 I/O38 I/O39 CLK0/I0 VCCO GND NC CLK1/I1 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND I/O50 I/O51 I/O52 I/O53 I/O54 NC I/O55 I/O56 I/O57 I/O58 I/O59 VCC0 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VCC VCC0 I/O19 I/O18 I/O17 I/O16 I/O15 NC I/O14 I/O13 I/O12 I/O11 I/O10 GND I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC0 GND VCC NC I/O159 I/O158 I/O157 I/O156 I/O155 NC I/O154 I/O153 I/O152 I/O151 I/O150 GND I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 NC GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VCCO I/O139 I/O138 I/O137 I/O136 I/O135 TDI I/O134 I/O133 I/O132 I/O131 I/O130 GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 CLK3/I4 VCC GND VCCO GND CLK2/I3 I/O119 I/O118 I/O117 I/O116 I/O115 NC I/O114 I/O113 I/O112 I/O111 I/O110 GND I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 GND 40 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 256-Ball PBGA (BG256) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A GND I/O21 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A B I/O23 I/O20 I/O19 I/O18 I/O15 I/O11 I/O8 I/O5 I/O1 I/O191 I/O187 I/O185 I/O181 NC NC I/O174 I/O171 I/O170 NC I/O166 B C NC NC I/O22 NC I/O17 I/O14 I/O10 I/O6 I/O2 NC I/O188 I/O184 I/O180 I/O179 I/O176 I/O173 I/O172 I/O167 I/O165 I/O162 C D I/O24 NC NC GND NC VCCO I/O13 GND I/O3 NC VCC I/O183 GND I/O177 VCCO NC GND I/O164 TDI I/O160 D E I/O27 I/O26 I/O25 NC I/O163 I/O161 I/O159 I/O156 E F I/O30 TCK I/O28 VCCO VCCO I/O158 NC I/O154 F G I/O33 I/O32 I/O31 I/O29 I/O157 I/O155 I/O153 I/O152 G H I/O35 NC I/O34 GND GND GND GND GND GND GND GND I/O151 I/O150 I/O149 H J I/O39 I/O38 I/O37 I/O36 GND GND GND GND GND GND I/O148 I/O147 I/O146 I/O145 J K I/O42 I/O40 I/O41 VCC GND GND GND GND GND GND I/O144 CLK3/I4 NC NC K L I/O43 I/O44 I/O45 I/O46 GND GND GND GND GND GND VCC CLK2/I3 I/O143 NC L M I/O47 CLK0/I0 CLK1/I1 I/O48 GND GND GND GND GND GND I/O139 I/O140 I/O141 I/O142 M N I/O49 I/O50 I/O51 GND GND GND GND GND GND GND GND I/O136 I/O137 I/O138 N P I/O52 I/O53 I/O55 I/O58 I/O131 I/O133 I/O134 I/O135 P R I/O54 I/O56 I/O59 VCCO VCCO I/O130 NC I/O132 R T I/O57 I/O60 I/O62 I/O65 I/O124 I/O127 I/O128 I/O129 T U I/O61 I/O63 I/O66 GND I/O76 VCCO I/O82 GND I/O91 VCC I/O98 I/O102 GND I/O112 VCCO NC GND I/O123 I/O122 I/O126 U V I/O64 I/O67 I/O69 I/O75 I/O78 I/O81 I/O85 I/O88 I/O92 I2 I/O97 I/O101 I/O105 I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 I/O95 I/O96 I/O100 I/O104 I/O107 I/O110 NC NC I/O115 I/O118 I/O120 W Y I/O71 I/O73 I/O77 TMS I/O80 I/O84 I/O87 I/O90 I/O94 NC NC I/O99 I/O103 I/O106 I/O108 I/O111 NC NC I/O116 I/O119 Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 *NOTE: Center pins must be connected to GND to aid thermal dissipation. 41 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 256-Ball Fine-Pitch BGA (BB256) Top View 1 A GND 2 GND 3 I/O26 4 I/O24 5 I/O20 6 VCC 7 I/O11 8 GND 9 GND 10 I/O186 11 VCC 12 I/O177 13 I/O172 14 I/O167 15 GND 16 GND B GND I/O27 I/O25 I/O23 I/O19 I/O15 I/O10 GND GND I/O185 I/O181 I/O176 I/O171 I/O166 I/O165 GND C I/O29 I/O28 NC I/O22 I/O18 I/O14 I/O9 I/O4 I/O191 I/O184 I/O180 I/O175 I/O170 NC I/O163 I/O164 D I/O32 I/O31 I/O30 NC I/O17 I/O13 I/O8 I/O3 I/O190 I/O183 I/O179 I/O174 I/O169 I/O160 I/O161 I/O162 E I/O35 I/O34 I/O33 I/O21 I/O16 I/O12 I/O7 I/O2 I/O189 VCC I/O178 I/O173 I/O168 I/O157 I/O158 I/O159 F VCC I/O38 I/O37 I/O36 TCLK VCC I/O6 I/O1 I/O188 I/O182 VCC TDI I/O154 I/O155 I/O156 VCC G I/O43 I/O42 I/O41 I/O40 VCC I/O39 I/O5 I/O0 I/O187 I/O148 I/O149 CLK3 /I4 CLK2 /I3 I2 I/O150 I/O151 I/O152 I/O153 H GND GND I/O47 I/O46 CLK0 /I0 NC I/O45 I/O44 GND GND I/O144 I/O145 I/O146 I/O147 GND GND J GND GND I/O51 I/O50 I/O49 I/O48 GND GND I/O140 I/O141 I/O142 I/O143 GND GND K I/O57 I/O56 I/O55 I/O54 CLK1 /I1 TMS I/O53 I/O52 I/O91 I/O96 I/O101 I/O135 VCC I/O136 I/O137 I/O138 I/O139 L VCC I/O60 I/O59 I/O58 VCC I/O86 I/O92 I/O97 I/O102 VCC TDO I/O132 I/O133 I/O134 VCC M I/O63 I/O62 I/O61 I/O72 I/O77 I/O82 VCC I/O93 I/O98 I/O103 I/O108 I/O112 I/O117 I/O129 I/O130 I/O131 N I/O66 I/O65 I/O64 I/O73 I/O78 I/O83 I/O87 I/O94 I/O99 I/O104 I/O109 I/O113 NC I/O126 I/O127 I/O128 P I/O68 I/O67 NC I/O74 I/O79 I/O84 I/O88 I/O95 I/O100 I/O105 I/O110 I/O114 I/O118 NC I/O124 I/O125 R GND I/O69 I/O70 I/O75 I/O80 I/O85 I/O89 GND GND I/O106 I/O111 I/O115 I/O119 I/O121 I/O123 GND T GND GND I/O71 I/O76 I/O81 VCC I/O90 GND GND I/O107 VCC I/O116 I/O120 I/O122 GND GND 42 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 352-Lead BGA (BG352) Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 2 3 4 5 6 7 8 9 10 11 I/O7 I/O8 I/O6 12 I/O4 I/O5 I/O3 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND GND I/O19 I/O15 I/O13 I/O34 I/O31 I/O28 I/O25 I/O 10 GND NC I/O18 I/O17 I/O14 I/O35 I/O32 I/O29 I/O26 I/O 11 I/O9 NC I/O1 I/O263 I/O 260 I/O257 I/O 254 I/O239 I/O 237 I/O232 I/O 229 I/O250 I/O 248 I/O244 GND GND I/O2 VCC I/O 261 I/O258 I/O 255 I/O252 I/O 234 I/O231 I/O 228 I/O249 I/O 246 I/O245 I/O 240 GND I/O23 I/O38 I/O37 I/O16 I/O12 I/O33 I/O30 I/O27 I/O24 I/O39 I/O40 I/O36 I/O42 TCK I/O41 NC NC NC I/O21 I/O20 VCCO VCCO I/O0 I/O262 I/O 259 I/O256 I/O 253 I/O238 I/O 235 I/O233 I/O 230 I/O251 I/O 247 I/O225 I/O 224 I/O227 NC VCCO VCCO I/O236 I/O 243 NC NC NC I/O226 I/O 222 I/O223 TDI I/O 221 I/O220 GND GND VCCO VCCO GND GND I/O45 I/O44 I/O43 I/O22 I/O48 I/O47 I/O46 I/O63 I/O49 I/O50 I/O51 VCCO I/O52 I/O53 I/O54 VCCO I/O55 I/O56 I/O57 I0 NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O 242 I/O219 I/O 218 I/O217 I/O 241 I/O216 I/O 215 I/O214 VCCO I/O211 I/O 212 I/O213 VCCO I/O208 I/O 209 I/O210 NC I/O205 I/O 206 I/O207 I4 I/O197 I/O59 I/O58 GND I1 GND GND I/O204 GND I3 I/O61 I/O60 I/O64 VCC I/O 203 I/O202 I/O62 VCCO VCCO I/O201 I/O 200 I/O199 VCCO I/O196 VCC I/O198 GND I/O193 I/O 194 I/O195 GND I/O178 I/O 179 I/O192 NC I/O177 I/O 176 I/O175 I/O65 I/O66 I/O67 VCCO I/O68 I/O69 I/O70 GND I/O71 I/O84 I/O85 GND I/O88 I/O87 I/O86 NC I/O91 I/O90 I/O89 VCCO I/O94 I/O93 I/O92 VCCO I/O95 I/O72 I/O73 I/O110 I/O74 I/O75 I/O76 I/O111 I/O77 I/O78 I/O79 N/C NC I/O112 I/O 113 VCCO VCCO NC GND GND VCCO VCCO GND GND I2 NC VCCO VCCO I/O150 I/O 151 NC VCCO I/O174 I/O 173 I/O172 VCCO I/O171 I/O 170 I/O169 I/O 153 I/O190 I/O 191 I/O168 I/O 152 I/O187 I/O 188 I/O189 NC NC I/O184 I/O 185 I/O186 I/O155 I/O 183 I/O182 I/O81 I/O80 I/O 108 N/C AD I/O 109 I/O82 I/O83 I/O117 I/O97 I/O100 I/O 102 I/O105 I/O 120 I/O123 I/O 126 I/O129 AE AF GND NC I/O133 I/O 136 I/O139 I/O 142 I/O157 I/O 159 I/O161 I/O 163 I/O166 I/O 146 I/O180 I/O 181 I/O154 NC GND I/O 115 I/O116 I/O 119 I/O98 I/O 101 I/O103 I/O 106 I/O121 I/O 124 I/O127 VCC I/O130 I/O 134 I/O137 I/O 140 I/O143 I/O 160 I/O162 I/O 165 I/O144 I/O 147 I/O148 GND GND I/O 114 I/O118 I/O96 I/O99 TMS I/O104 I/O 107 I/O122 I/O 125 I/O128 I/O 131 I/O132 I/O 135 I/O138 I/O 141 I/O156 I/O 158 TDO I/O 164 I/O167 I/O 145 I/O149 GND GND *NOTE: Center pins must be connected to GND to aid thermal dissipation. 43 ULTRA37000TM CPLD Family[1] Pin Configurations[18] (continued) 400-Ball Fine-Pitch BGA (BB400) Top View A GND GND NC I/O17 I/O16 I/O14 I/O29 VCC I/O11 GND GND I/O257 VCC I/O239 I/O233 I/O232 I/O230 NC GND GND B GND GND GND NC I/O15 I/O13 I/O28 VCC I/O10 GND GND I/O256 VCC I/O238 I/O231 I/O229 NC GND GND GND C NC GND GND GND I/O20 I/O12 I/O27 VCC I/O9 GND GND I/O255 VCC I/O237 I/O228 I/O245 GND GND GND NC D I/O44 NC GND I/O21 I/O19 I/O18 I/O26 I/O25 I/O8 GND GND I/O254 I/O235 I/O236 I/O251 I/O244 I/O243 GND NC I/O227 E I/O46 I/O43 I/O23 I/O22 NC I/O35 I/O34 I/O24 I/O7 I/O4 I/O263 I/O253 I/O234 I/O250 I/O248 NC I/O241 I/O242 I/O225 I/O226 F I/O47 I/O45 I/O42 I/O41 I/O40 NC I/O33 I/O32 I/O6 I/O3 I/O262 I/O252 I/O249 I/O247 I/O220 I/O221 I/O240 I/O222 I/O223 I/O224 G I/O53 I/O52 I/O51 I/O50 I/O39 I/O38 I/O37 I/O31 I/O5 I/O2 I/O261 VCC I/O246 I/O217 I/O218 I/O219 I/O212 I/O213 I/O214 I/O215 H VCC VCC VCC I/O49 I/O48 I/O36 TCLK VCC I/O30 I/O1 I/O259 I/O260 VCC TDI I/O216 I/O210 I/O211 VCC VCC VCC J I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 VCC I/O62 I/O60 I/O0 I/O258 I/O202 I/O203 CLK3 /I4 CLK2 /I3 I2 I/O204 I/O205 I/O206 I/O207 I/O208 I/O209 K GND GND GND GND I/O65 I/O64 CLK0 /I0 NC I/O63 I/O61 GND GND I/O198 I/O199 I/O200 I/O201 GND GND GND GND L GND GND GND GND I/O69 I/O68 I/O67 I/O66 GND GND I/O193 I/O195 I/O196 I/O197 GND GND GND GND M I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 CLK1 /I1 TMS I/O71 I/O70 I/O126 I/O132 I/O192 I/O194 VCC I/O174 I/O175 I/O176 I/O177 I/O178 I/O179 N VCC VCC VCC I/O91 I/O90 I/O72 VCC I/O128 I/O127 I/O133 I/O162 VCC TDO I/O180 I/O168 I/O169 VCC VCC VCC P I/O95 I/O94 I/O93 I/O92 I/O75 I/O74 I/O73 I/O114 VCC I/O129 I/O134 I/O137 I/O163 I/O181 I/O182 I/O183 I/O170 I/O171 I/O172 I/O173 R I/O80 I/O79 I/O78 I/O108 I/O77 I/O76 I/O115 I/O117 I/O120 I/O130 I/O135 I/O138 I/O164 I/O165 NC I/O184 I/O185 I/O186 I/O189 I/O191 T I/O82 I/O81 I/O110 I/O109 NC I/O116 I/O118 I/O102 I/O121 I/O131 I/O136 I/O139 I/O156 I/O166 I/O167 NC I/O154 I/O155 I/O187 I/O190 U I/O83 NC GND I/O111 I/O112 I/O119 I/O104 I/O103 I/O122 GND GND I/O140 I/O157 I/O158 I/O150 I/O151 I/O153 GND NC I/O188 V NC GND GND GND I/O113 I/O96 I/O105 VCC I/O123 GND GND I/O141 VCC I/O159 I/O144 I/O152 GND GND GND NC W GND GND GND NC I/O97 I/O99 I/O106 VCC I/O124 GND GND I/O142 VCC I/O160 I/O145 I/O147 NC GND GND GND Y GND GND NC I/O98 I/O100 I/O101 I/O107 VCC I/O125 GND GND I/O143 VCC I/O161 I/O146 I/O148 I/O149 NC GND GND 44 ULTRA37000TM CPLD Family[1] Ordering Information CY 37 512 V P400 - 83 BB C Cypress Semiconductor ID Family Type 37 = ULTRA37000 Family Macrocell Density 32 = 32 Macrocells 64 = 64 Macrocells 128 = 128 Macrocells 192 = 192 Macrocells Operating Conditions Commercial 0C to +70C Industrial -40C to +85C Military - 5 5 C t o + 1 2 5 C 256 = 256 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells Package Type A = Thin Quad Flat Pack (TQFP) U = Ceramic Quad Flat Pack (CQFP) N = Plastic Quad Flat Pack (PQFP) NT = Thermally Enhanced Plastic Quad Flat Pack (EQFP) J = Plastic Leaded Chip Carrier (PLCC) Y = Ceramic Leaded Chip Carrier (CLCC) BG = Ball Grid Array (BGA) BA = Fine-Pitch Ball Grid Array (FBGA) 0.8mm Lead Pitch BB = Fine-Pitch Ball Grid Array (FBGA) 1.0mm Lead Pitch Speed 200 167 154 143 = = = = 200 167 154 143 MHz MHz MHz MHz 125 = 125 MHz 100 = 100 MHz 83 = 83 MHz 66 = 66 MHz Operating Reference Voltage V = 3.3V Supply Voltage (5.0V if not specified) Pin Count P44 = 44 Leads P48 = 48 Leads P84 = 84 Leads P100 = 100 Leads P160 = 160 Leads P208 = 208 Leads P256 = 256 Leads P352 = 352 Leads P400 = 400 Leads 5.0V Ordering Information Macrocells 32 Speed (MHz) 200 154 Ordering Code CY37032P44-200AC CY37032P44-200JC CY37032P44-154AC CY37032P44-154JC CY37032P44-154AI CY37032P44-154JI 125 CY37032P44-125AC CY37032P44-125JC CY37032P44-125AI CY37032P44-125JI Package Name A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 Package Type 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Operating Range Commercial 45 ULTRA37000TM CPLD Family[1] 5.0V Ordering Information (continued) Macrocells 64 Speed (MHz) 200 Ordering Code CY37064P44-200AC CY37064P44-200JC CY37064P84-200JC CY37064P100-200AC 154 CY37064P44-154AC CY37064P44-154JC CY37064P84-154JC CY37064P100-154AC CY37064P44-154AI CY37064P44-154JI CY37064P84-154JI CY37064P100-154AI CY37064P44-154YMB 125 CY37064P44-125AC CY37064P44-125JC CY37064P84-125JC CY37064P100-125AC CY37064P44-125AI CY37064P44-125JI CY37064P84-125JI CY37064P100-125AI CY37064P44-125YMB 128 167 CY37128P84-167JC CY37128P100-167AC CY37128P160-167AC 125 CY37128P84-125JC CY37128P100-125AC CY37128P160-125AC CY37128P84-125JI CY37128P100-125AI CY37128P160-125AI CY37128P84-125YMB 100 CY37128P84-100JC CY37128P100-100AC CY37128P160-100AC CY37128P84-100JI CY37128P100-100AI CY37128P160-100AI CY37128P84-100YMB Package Name A44 J67 J83 A100 A44 J67 J83 A100 A44 J67 J83 A100 Y67 A44 J67 J83 A100 A44 J67 J83 A100 Y67 J83 A100 A160 J83 A100 A160 J83 A100 A160 Y84 J83 A100 A160 J83 A100 A160 Y84 Package Type 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 44-Lead Ceramic Leadless Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 44-Lead Ceramic Leadless Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 84-Lead Ceramic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 84-Lead Ceramic Leaded Chip Carrier Military Industrial Military Commercial Industrial Commercial Military Commercial Industrial Military Commercial Industrial Commercial Operating Range Commercial 46 ULTRA37000TM CPLD Family[1] 5.0V Ordering Information (continued) Macrocells 192 Speed (MHz) 154 125 83 256 154 Ordering Code CY37192P160-154AC CY37192P160-125AC CY37192P160-125AI CY37192P160-83AC CY37192P160-83AI CY37256P160-154AC CY37256P208-154NC CY37256P256-154BGC 125 CY37256P160-125AC CY37256P208-125NC CY37256P256-125BGC CY37256P160-125AI CY37256P208-125NI CY37256P256-125BGI CY37256P160-125UMB 83 CY37256P160-83AC CY37256P208-83NC CY37256P256-83BGC CY37256P160-83AI CY37256P208-83NI CY37256P256-83BGI CY37256P160-83UMB 384 125 100 CY37384P208-125NC CY37384P256-125BGC CY37384P208-100NC CY37384P256-100BGC CY37384P208-100NI CY37384P256-100BGI 83 CY37384P208-83NC CY37384P256-83BGC CY37384P208-83NI CY37384P256-83BGI Package Name A160 A160 A160 A160 A160 A160 N208 BG256 A160 N208 BG256 A160 N208 BG256 U162 A160 N208 BG256 A160 N208 BG256 U162 N208 BG256 N208 BG256 N208 BG256 N208 BG256 N208 BG256 Package Type 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 160-Lead Ceramic Quad Flat Pack 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 160-Lead Ceramic Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array Industrial Commercial Industrial Commercial Military Commercial Industrial Military Commercial Industrial Commercial Operating Range Commercial Commercial Industrial Commercial Industrial Commercial 47 ULTRA37000TM CPLD Family[1] 5.0V Ordering Information (continued) Macrocells 512 Speed (MHz) 125 Ordering Code CY37512P208-125NC CY37512P208-125NTC CY37512P256-125BGC CY37512P352-125BGC 100 CY37512P208-100NC CY37512P208-100NTC CY37512P256-100BGC CY37512P352-100BGC CY37512P208-100NI CY37512P208-100NTI CY37512P256-100BGI CY37512P352-100BGI CY37512P208-100UMB 83 CY37512P208-83NC CY37512P208-83NTC CY37512P256-83BGC CY37512P352-83BGC CY37512P208-83NI CY37512P208-83NTI CY37512P256-83BGI CY37512P352-83BGI CY37512P208-83UMB Package Name N208 NT208 BG256 BG352 N208 NT208 BG256 BG352 N208 NT208 BG256 BG352 U208 N208 NT208 BG256 BG352 N208 NT208 BG256 BG352 U208 Package Type 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 208-Lead Ceramic Quad Flat Pack 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 208-Lead Ceramic Quad Flat Pack Military Industrial Military Commercial Industrial Commercial Operating Range Commercial 3.3V Ordering Information Macrocells 32 Speed (MHz) 143 100 Ordering Code CY37032VP44-143AC CY37032VP44-143JC CY37032VP44-100AC CY37032VP44-100JC CY37032VP44-100AI CY37032VP44-100JI Package Name A44 J67 A44 J67 A44 J67 Package Type 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier Industrial Commercial Operating Range Commercial 48 ULTRA37000TM CPLD Family[1] 3.3V Ordering Information (continued) Macrocells 64 Speed (MHz) 143 Ordering Code CY37064VP44-143AC CY37064VP44-143JC CY37064VP48-143BAC CY37064VP84-143JC CY37064VP100-143AC 100 CY37064VP44-100AC CY37064VP44-100JC CY37064VP48-100BAC CY37064VP84-100JC CY37064VP100-100AC CY37064VP44-100AI CY37064VP44-100JI CY37064VP48-100BAI CY37064VP84-100JI CY37064VP100-100AI CY37064VP44-YMB 128 125 CY37128VP84-125JC CY37128VP100-125AC CY37128VP100-125BBC CY37128VP160-125AC 83 CY37128VP84-83JC CY37128VP100-83AC CY37128VP100-83BBC CY37128VP160-83AC CY37128VP84-83JI CY37128VP100-83AI CY37128VP100-83BBI CY37128VP160-83AI CY37128VP84-83YMB 192 100 66 CY37192VP160-100AC CY37192VP160-66AC CY37192VP160-66AI Package Name A44 J67 BA48 J83 A100 A44 J67 BA48 J83 A100 A44 J67 BA48 J83 A100 Y67 J83 A100 BB100 A160 J83 A100 BB100 A160 J83 A100 BB100 A160 Y84 A160 A160 A160 Package Type 44-Lead Thin Quad Flatpack 44-Lead Plastic Leaded Chip Carrier 48-Lead Fine-Pitch Ball Grid Array 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flatpack 44-Lead Thin Quad Flatpack 44-Lead Plastic Leaded Chip Carrier 48-Lead Fine-Pitch Ball Grid Array 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flatpack 44-Lead Thin Quad Flatpack 44-Lead Plastic Leaded Chip Carrier 48-Lead Fine-Pitch Ball Grid Array 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flatpack 44-Lead Ceramic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 100-Lead Fine-Pitch Ball Grid Array 160-Lead Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 100-Lead Fine-Pitch Ball Grid Array 160-Lead Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Lead Thin Quad Flat Pack 100-Lead Fine-Pitch Ball Grid Array 160-Lead Thin Quad Flat Pack 84-Lead Ceramic Leaded Chip Carrier 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack 160-Lead Thin Quad Flat Pack Military Commercial Commercial Industrial Industrial Commercial Military Commercial Industrial Commercial Operating Range Commercial 49 ULTRA37000TM CPLD Family[1] 3.3V Ordering Information (continued) Macrocells 256 Speed (MHz) 100 Ordering Code CY37256VP160-100AC CY37256VP208-100NC CY37256VP256-100BGC CY37256VP256-100BBC 66 CY37256VP160-66AC CY37256VP208-66NC CY37256VP256-66BGC CY37256VP256-66BBC CY37256VP160-66AI CY37256VP256-66BGI CY37256VP256-66BBI CY37256VP160-66UMB 384 83 66 CY37384VP208-83NC CY37384VP256-83BGC CY37384VP208-66NC CY37384VP256-66BGC CY37384VP208-66NI CY37384VP256-66BGI 512 83 CY37512VP208-83NC CY37512VP208-83NTC CY37512VP256-83BGC CY37512VP352-83BGC CY37512VP400-83BBC 66 CY37512VP208-66NC CY37512VP208-66NTC CY37512VP256-66BGC CY37512VP352-66BGC CY37512VP400-66BBC CY37512VP208-66NI CY37512VP208-66NTI CY37512VP256-66BGI CY37512VP352-66BGI CY37512VP400-66BBI CY37512VP208-66UMB Package Name A160 N208 BG256 BB256 A160 N208 BG256 BB256 A160 BG256 BB256 U162 N208 BG256 N208 BG256 N208 BG256 N208 NT208 BG256 BG352 BB400 N208 NT208 BG256 BG352 BB400 N208 NT208 BG256 BG352 BB400 U208 Package Type 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 256-Lead Fine-Pitch Ball Grid Array 160-Lead Thin Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 256-Lead Fine-Pitch Ball Grid Array 160-Lead Thin Quad Flat Pack 256-Lead Ball Grid Array 256-Lead Fine-Pitch Ball Grid Array 160-Lead Ceramic Quad Flat Pack 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 400-Lead Fine-Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 400-Lead Fine-Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Thermally Enhanced Plastic Quad Flat Pack 256-Lead Ball Grid Array 352-Lead Ball Grid Array 400-Lead Fine-Pitch Ball Grid Array 208-Lead Ceramic Quad Flat Pack Military Industrial Commercial Commercial Industrial Commercial Military Commercial Industrial Commercial Operating Range Commercial In-System Reprogrammable, ISR, ULTRA37000, and Warp are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Document #: 38-00475-G 50 ULTRA37000TM CPLD Family[1] Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-B 51 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B 52 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 160-Pin Thin Plastic Quad Flat Pack (TQFP) A160 51-85049-A 53 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 48-Ball Thin Ball Grid Array (7 x 7 x 1.1 mm, 0.8 pitch) BA48 51-85109 54 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107 55 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 256-Ball Thin Ball Grid Array (17 x 17 x 1.4 mm) BB256 51-85108 56 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 400-Ball FBGA (21 x 21 x 1.4 mm) BB400 51-85111 57 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 58 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 352-Lead Ball Grid Array (35 x 35 x 2.33 mm) BG352 51-85103 59 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 44-Lead Plastic Leaded Chip Carrier J67 51-85003-A 84-Lead Plastic Leaded Chip Carrier J83 51-85006-A 60 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 208-Lead Plastic Quad Flatpack N208/NT208 51-85069-B 61 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 160-Lead Ceramic Quad Flatpack (Cavity Up) U162 51-80106 62 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 208-Lead Ceramic Quad Flatpack (Cavity Up) U208 51-80105 63 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 44-Pin Ceramic Leaded Chip Carrier Y67 51-80014 64 ULTRA37000TM CPLD Family[1] Package Diagrams (continued) 84-Pin Ceramic Leaded Chip Carrier Y84 51-80095-A (c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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